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If you could somehow generate a MHz clock from the 50 MHz clock on the board, you could avoid using two different clock sources in your system, and you also would not have to operate the board at a higher-than-necessary frequency. We can identify another application of clock synthesis if we recall that some digital signal processing DSP applications are multirate and require different clock frequencies in different parts of the algorithm. Different vendors use different terms to refer to their CMBs. The CMBs can generate new clock signals by performing clock multiplication and division.

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They may be able to apply a programmable phase shift to a generated clock or even adjust the duty cycle of a clock. One application for the programmable phase shift feature is synchronizing the clock signal with input data. Without this phase shift capability, the clock may not fall at the center of the data eye.

These dedicated buffers and routes enable us to have a low-skew clock network. In this way, the circuit compensates for the delay in the clock distribution network, and theoretically we can de-skew the clock distribution. So, how can the block diagram of Figure 2 eliminate the clock skew?

How can we circumvent the problem of creating a negative delay?

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Remember that the clock signal is a periodic waveform. This is illustrated in Figure 4.

On the other hand, a PLL is more flexible when synthesizing new clock signals. Note that the CMBs can de-skew not only the clock signals distributed within the FPGA but also the clocks going to other devices on the board. We saw that the CMBs can be used to synthesize new clock signals.

Integrated Time & Frequency Systems

These resources are responsible for distributing high-fanout clock signals with a low skew. To distribute a clock signal to all parts of a chip with equal propagation delays, we can use a special form of routing called an H tree. You can see an example in Figure 6.

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Therefore, theoretically, all the clocked elements will see the same clock signal. The Intel devices also have periphery clock PCLK networks that are distributed in a smaller area of the chip.

High Performance Clock Distribution Networks

An example is shown in Figure 9 below. As shown in Figures 8 and 9, FPGAs have dedicated clock routes that are distributed in just one region of the chip. These are called clock regions. Note that different devices have different clock regions.


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Also note that we need some buffers to efficiently distribute a clock signal along the dedicated routes that we discussed above. Power tradeoffs of the proposed design techniques are investigated and physical layout information is incorporated to synthesize the clock tree layout based on a set of benchmark circuits. This book provides the reader with information on those effects that introduce delay uncertainty and with the tools to successfully design high performance synchronous circuits.


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  6. The original research presented in this book has been awarded with the Outstanding Dissertation Award by the European Design Automation Association. Toggle navigation. Login Username. Lambert Academic Publishing on facebook.